Wednesday, 17 July 2019

Introduction to Makefile




make utility is a build automation tool typically used to read the list of code source files and compilation, linking and building rules in order to create executables and/or libraries. As it's capable of running an arbitrary shell commands and applications, it is possible to use it as a general automation tool. 

make reads Makefile in order to find out which files it should operate on and which commands should be run.

Makefile consists of a list of so called targets (or recipies) which come in form:

target: dependency1 dependency2 ...
        command1
        command2
        ...

target can be:
  • name of the output file which is usually a binary or object file
  • name of the arbitrary action e.g. clean, linter etc. 
dependency:
  • can be:
    • names of files which are used as inputs in creating the target file
    • names of previously defined targets 
  • dependencies are optional, they can be omitted in which case the command needs to be in the next line
comand
  • must be written in its own line; if long, it can be break into new line with backslash character
  • each command line needs to start with TAB character
  • commands are optional in which case the list of dependencies goes in the same line as target label unless backslash is used to break dependencies list into multiple lines

If there are no commands but only dependencies:

target: dependency1 dependency2 ...

If we want to list each dependency in a separate line we can use backslash character to break lines (note that there is a backslash in each line apart the last!)

target: \
    dependency1 \
    dependency2


If there are no dependencies but only commands:

target:
    command1
    command2
    ...


If target is the name of an arbitrary action it is called phony and we need to explicitly tell Make that it's not associated with some file:

.PHONY: action
action:
        command1
        command2



To test the Makefile target syntax, run:

make my_target --dry-run


To run the target:

make my_target

make commands


ifeq
else
endif
...

They MUST NOT be indented with TAB characters as (almost) all lines with TAB characters as the first character on the line in a makefile are passed to the shell (/bin/sh). The shell doesn't know anything about  make commands. make commands can be indented with a set of SPACE characters but this might be misleading as recipies is what MUST be indented with TABs.


Recipies


They must be indented with TAB character in order to be passed to shell.

Targets


Targets are labels that allow make to execute a group of commands together.

Makefile:

target1:
   @echo target1 is executing
target2:
   @echo target2 is executing

We can now run make as:

$ make target1

or

$ make target2

Minimal (but working) example of Makefile:

docker-run:
@echo Building and running Docker image...
docker build -t cpp-demo . && docker run --rm --name cpp-demo cpp-demo

To run it:

$ make docker-run 

Conditional Execution


Use ifeq-endif or ifeq-else-endif blocks.

Makefile:

VAR1= test
VAR2=nottest

demo-if-else-endif:

ifeq($(VAR1), $(VAR2))
   ...
else
   ...
endif

Makefile ifeq: when are they evaluated?

Variable comparison


TEST=ON
ifeq ($(TEST),ON)
    @echo PASSED
else
    @echo FAILED
endif


To check if variable is empty:

ifeq ($(TEST),)
TEST := $(something else)
endif

Makefile set if variable is empty

 

Using Makefile in Docker projects




Resources:


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